À×»ð

  • 11.jpg 12.jpg

    SALDRAGON 1

    ¹¤Òµ¿ØÖÆ¡¢»úÆ÷ÊÓ¾õ¡¢ÄÜÔ´µçÁ¦¡¢Æû³µµç×Ó

    ²úÆ·¼ò½é

    À×»ðSALDRAGON 1£¨ÒÔϼò³Æ DR1£©ÏµÁÐÆ÷¼þÑÓÐø°²Â·FPSoC¼Ò×壬×éºÏÁËÓ²ºË´¦ÀíÆ÷ϵͳºÍFPGA£¬Í¨¹ý¸ß´ø¿í×ÜÏß½øÐжþÕߵĻ¥Áª¡£¶àºË ARM/RISC-V ´¦ÀíÆ÷ϵͳÓ밲·FPGA¿É±à³ÌÂß¼­Ïà½áºÏÓÚÒ»¿ÅоƬÖУ¬ÌṩÁËÓ¦ÓÃÀàARM/RISC-V´¦ÀíÆ÷µÄÐÔÄÜ ÓëÉú̬ϵͳ£¬²¢ÇҾ߱¸°²Â·FPGAµÄÁé»îÐÔ¡¢µÍ¹¦ºÄ¡¢¿ÉÀ©Õ¹ SoCƽ̨¡£ARM/RISC-V CPUÊÇ´¦ÀíÆ÷ϵͳµÄºËÐÄ£¬Í¬Ê±ÏµÍ³»¹°üº¬on-chip RAM£¬ÄÚ´æ½Ó¿ÚºÍ·á¸»µÄÍâÉ軥Áª½Ó¿Ú£¬¶¨Î»¸´ÔÓǶÈëʽϵͳ¡¢µÍ¹¦ºÄºÍ¸ßÐÔÄÜоƬÊг¡¡£

    ²úÆ·Ñ¡Ðͱí

    ÏÔʾ6ÖÖ²úÆ·
    Device Processor Core Processor Extensions Maximum Frequency£¨MHz£© Cache/TCM On-Chip RAM SDRAM Peripherals Peripherals w/built-in DMA PS-PL Interface Ports DMA Channels JPU NPU TIMER PS IO2 External Static Memory Support LUTs DFFs DistributeRAM eRAM-20K eRAM-Total DSP PLL TS ADC MIPI DPHY-RX MAX user IO
    DR1M90MEG484 Ë«ºË ARM ´¦ÀíÆ÷ NEON & Single / Double Precision Floating Point for each processor 1000 L1:32 KB Instruction,32 KB data per processor ; L2:512 KB 256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬AXI 64-bit ACP£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM ARM ͨÓö¨Ê±Æ÷£¬ ϵͳ¼¶ Triple-timer ¼ÆÊýÆ÷, ¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 2 195
    DR1M90GEG484 Ë«ºË ARM ´¦ÀíÆ÷ NEON & Single / Double Precision Floating Point for each processor 1000 L1:32 KB Instruction,32 KB data per processor ; L2:512 KB 256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬AXI 64-bit ACP£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM ARM ͨÓö¨Ê±Æ÷£¬ ϵͳ¼¶ Triple-timer ¼ÆÊýÆ÷, ¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 - 201
    DR1V90MEG484 µ¥ºË RISC-V ´¦ÀíÆ÷ P/F/D Instruction Extension 800 L1:32 KB Instruction,32 KB data per processor
    ITCM£º256KB
    DTCM1£º256KB
    256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬32-bit AHB£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM RISC-V ¶¨Ê±Æ÷£¬ÏµÍ³¼¶ Triple-timer ¼ÆÊýÆ÷£¬¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 2 195
    DR1V90GEG484 µ¥ºË RISC-V ´¦ÀíÆ÷ P/F/D Instruction Extension 800 L1:32 KB Instruction,32 KB data per processor
    ITCM£º256KB
    DTCM1£º256KB
    256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬32-bit AHB£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM RISC-V ¶¨Ê±Æ÷£¬ÏµÍ³¼¶ Triple-timer ¼ÆÊýÆ÷£¬¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 - 201
    DR1V90GEG400 µ¥ºË RISC-V ´¦ÀíÆ÷ P/F/D Instruction Extension 800 L1:32 KB Instruction,32 KB data per processor
    ITCM£º256KB
    DTCM1£º256KB
    256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬32-bit AHB£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM RISC-V ¶¨Ê±Æ÷£¬ÏµÍ³¼¶ Triple-timer ¼ÆÊýÆ÷£¬¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 - 126
    DR1M90GEG400 Ë«ºË ARM ´¦ÀíÆ÷ NEON & Single / Double Precision Floating Point for each processor 1000 L1:32 KB Instruction,32 KB data per processor ; L2:512 KB 256KB 16/32-bit DDR3/DDR3L/DDR4 UART,CAN 2.0B/FD,I2C,SPI,GPIO USB 2.0Tri-mode Gigabit Ethernet£¬SD4.2/SDIO/eMMC5.1 ¿ØÖÆÆ÷ AXI 32-bit Master£¬AXI 32-bit Slave£¬AXI 64-bit/32-bit Memory(HP)£¬AXI 64-bit ACP£¬16 Interrupts 8(4 dedicated to Programmable Logic) JPEG baseline encoder/decoder 512x MAC,0.4TOPs,256KB SRAM ARM ͨÓö¨Ê±Æ÷£¬ ϵͳ¼¶ Triple-timer ¼ÆÊýÆ÷, ¿´ÃŹ·¶¨Ê±Æ÷ 54 Quad-SPI£¬NAND 94464 104960 1340 280 5600 240 8 2 1 - 126
    • ²úÆ·ÌØÉ«
    • Ó¦Óó¡¾°
    • ×ÊÁÏÏÂÔØ

    ²úÆ·ÌØÉ«

    • Èí¡¢Ó²¼þ¿É±à³Ì FPSoCƽ̨

      Ë«ºËARM Cortex-A35 64λ´¦ÀíÆ÷ µ¥ºËRISC-V 64λ´¦ÀíÆ÷

    • ¸ßÐÔÄÜ´óÈÝÁ¿¿ÉÅäÖÃÂß¼­Ä£¿é

      µÈЧÂß¼­µ¥Ôª£º95K (LUT4 Âß¼­×ÊÔ´ )

    • Ö§³ÖDDR3ºÍDDR4´æ´¢½Ó¿Ú

      ×î´óÖ§³Ö1333Mbps£¬Î»¿í x32

    • SEU¼ì´íºÍ¾À´í

      Ö§³Öµ¥bit¼ì´íºÍ¾À´í¡¢Ö§³ÖË«bit¼ì´í

    • ¼¯³ÉMIPI D-PHY

      Ö§³Ö¸ß´ø¿íÊÓÆµÊäÈë

    ×ÊÁÏÏÂÔØ

    µã»÷·´À¡ÄúµÄÐèÇó£¬ÖúÁ¦À×»ðÊ×Ò³´òÔì¸üÓÅÖʵÄFPGA²úÆ·£¡

    ¶©ÔÄÐÅÏ¢
    a1_icon02.svg
    download.jpg
    a1_icon03.svg
    a1_icon01.svg
    Frame.svg

    ¶©ÔÄ

    µØÇø

    §h

    ÎÒÒÑ×ÐϸÔĶÁ²¢Í¬ÒâÒþ˽ÉùÃ÷

    ¶Ô²»Æð£¬ÄúÉÐδµÇ¼£¡

    À×»ðÊ×Ò³ÌṩÁËEF2\EF3\EG4µÈϵÁÐÆ÷¼þµÄFamilyOverviewÎĵµ£¬¿ÉÃâ×¢²áµÇ¼ÏÂÔØ¡£

    ÈçÐ迪ͨ×ÊÁÏȨÏÞ£¬Ç뽫¾ßÌåÐèÇó¼°»áÔ±×¢²áÊÖ»úºÅ·¢Ë͵½ÈçÏÂÓÊÏ䣬¿Í·þÈËÔ±»á¾¡¿ì´¦Àí¡£

    ¶Ô²»Æð£¬ÄúµÄ»áÔ±µÈ¼¶²»×㣡

    ÈçÐ迪ͨȨÏÞ£¬ÇëÏȵǼ»áÔ±ÍêÉÆ¸öÈËÐÅÏ¢£¬ÔÙ½«¾ßÌåÐèÇó¼°×¢²áÊÖ»úºÅ·¢Ë͵½ÈçÏÂÓÊÏ䣬¿Í·þÈËÔ±»á¾¡¿ì´¦Àí¡£

    ¡¾ÍøÕ¾µØÍ¼¡¿¡¾sitemap¡¿